Method of simultaneously making a pair of transistors with insulated gates having respectively a thin oxide and a thick oxide, and corresponding integrated circuit comprising such a pair of transistors

ABSTRACT

A method of simultaneously fabricating a pair of insulated gate transistors respectively having a thin oxide and a thick oxide, and an integrated circuit including a pair of transistors of this kind. Forming low-doped NLDD areas of the thin oxide second transistor includes implanting a first dopant having a first concentration and implanting a second dopant having a second concentration lower than the first concentration. Forming low-doped areas NLDD of the first, thick oxide transistor includes only said implantation of the second dopant.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a national state entry of application PCT/FR01/03343filed on Oct. 26, 2001, which is based upon and claims priority fromprior French Patent Application No. 0013949, filed Oct. 30, 2000, thedisclosure of each application which is hereby incorporated by referenceindividually in its entirety.

The invention relates to microelectronics, in particular to fabricatingintegrated circuits, and more particularly to fabricating a pair ofinsulated gate transistors simultaneously by a process known in the artas the “double gate oxide” process.

The “double gate oxide” process forms simultaneously a first transistorhaving a thick gate oxide layer, for example a layer having a thicknessof the order of 120 Å, and a second transistor having a thin gate oxidelayer (i.e. a layer thinner than the gate oxide of the firsttransistor), for example a layer having a thickness of the order of 50Å.

A thin oxide transistor can be used to implement logic functions. Athick oxide transistor operates at higher voltages than thin oxidetransistors, for example 5 volts, and can be used to implement analogfunctions.

The skilled person knows that an insulated gate transistor hashigh-doped drain and source regions and low-doped source and drain (LowDoped Drain—LDD) areas extending under the lateral insulative regions(spacers) of the transistor between the high-doped drain and sourceregions and the channel region of the transistor. The thin oxidetransistor requires an abrupt transition between the low-doped sourceand drain area and the channel region to reduce its input/outputresistance and short channel effects.

However, in the gate double oxide process usually employed, thelow-doped source and drain areas are implanted not only for the thinoxide transistor but also for the thick oxide transistor. For the thickoxide transistor, operating at higher voltages, the sudden transitioncaused by implanting the low-doped source and drain regions causes aproblem of leakage in the turned off state, known as gate-induced drainleakage (GIDL), and a reliability problem (hot carriers).

The invention aims to provide a solution to this problem.

The invention aims to improve the “gate double oxide” process so that athin oxide transistor and a thick oxide transistor can be madesimultaneously without degrading the performance of the thin oxidetransistor and which improves the performance of the thick oxidetransistor in terms of gate-induced drain linkage (GIDL) andreliability.

Another object of the invention is to offer this improvement at reducedcost.

The invention therefore proposes a method of simultaneously fabricatinga pair of insulated gate transistors, a first transistor of the pairhaving a thicker gate oxide layer than the second transistor of thepair. The method includes, for each transistor, forming the gate oxidelayer, forming the gate flanked by insulative lateral regions, forminghigh-doped drain and source regions, and forming low-doped source anddrain areas extending under the insulative lateral regions between thehigh-doped drain and source regions and the channel region of thetransistor.

According to one general feature of the invention, forming source anddrain areas of the second transistor (i.e. the thin oxide transistor)includes implanting a first dopant having a first concentration andimplanting a second dopant having a second concentration lower than thefirst concentration. Also, forming the source and drain areas of thefirst transistor (i.e. the thick oxide transistor) includes onlyimplanting the second dopant.

In one embodiment of the method, the first dopant is implanted on eitherside of the gate of the second transistor (thin oxide transistor) beforeforming the insulative lateral regions, the active area of the firsttransistor (thick oxide transistor) being protected by a layer of resin.The second dopant is implanted obliquely, for example at 45°, andsimultaneously from either side of insulative lateral regions associatedwith the gates of the two transistors.

The first and second transistors can both be N-channel transistors (NMOStransistors). In this case the first dopant can be arsenic and thesecond dopant can be phosphorus. Both dopants can be arsenic, however.

If phosphorus and arsenic are used, for example, the phosphorus NLDDjunction of the thick gate oxide transistor is gradual and the NLDDjunction of the thin gate oxide transistor, consisting of phosphorus andarsenic, is still abrupt.

The first and second transistors can equally well be P-channeltransistors (PMOS transistors). In this case the first dopant and thesecond dopant are advantageously the same and consist of boron.

The invention also provides an integrated circuit including at least onepair of insulated gate transistors fabricated by the above method.

Other advantages and features of the invention will become apparent onreading the following description of non-limiting embodiments of theinvention and from the accompanying drawings, in which FIGS. 1 to 15show diagrammatically the principal steps of one embodiment of a processaccording to the invention for obtaining a pair of transistors accordingto the invention.

FIG. 1 shows an initial silicon substrate 10, for example a P-typesubstrate.

Buried P-type layers 11 have been formed in the substrate 10 by aconventional manner known in the art.

An N silicon layer has then been grown epitaxially, again in aconventional manner known in the art, and etched locally to formtrenches. Insulative regions 15 are obtained after filling the trencheswith an oxide and polishing mechanically and chemically.

After protecting the future active area of the thick oxide transistorwith a layer of resin, conventional boron implantation has formed aP-type well 13 and P-type channel stops 12.

After protecting the wells 13 with a layer of resin, further P-typeimplantation in the active area of the future thick oxide transistor hasproduced another well 14. This implantation step, which is very familiarto the skilled person, adjusts the threshold voltage of the future thickoxide transistor to a relatively low value.

All the steps outlined above are very familiar to the skilled person andyield a substrate 1.

A first oxide layer 2, for example a layer of silicon oxide,approximately 100 Å thick is then grown on the top surface of thesubstrate 1.

After protecting the part 20 of the oxide layer 2 situated above thewell 14 between the two insulative areas 15 with a block 3 of resin, thelayer 2 is then partially etched, as shown in FIG. 2.

After removing the resin block 3 (FIG. 3), a 50 Å thick second oxidelayer 4 (for example of SiO₂) is grown on the top surface of thesubstrate 1 and on the top surface of the residual portion 20 of theoxide layer 2.

Growing the oxide layer 4 on the top surface of the silicon produces aportion 40 which is 50 Å thick. Growing the layer 4 on the residualportion 20 of silicon dioxide produces a portion 41 of silicon dioxidewhich is only about 20 Å thick.

The thickness of the gate oxide 2041 above the well 14 (FIG. 4) istherefore approximately 120 Å. The gate oxide 40 above the well 13 has athickness of the order of 50 Å.

A polysilicon layer 5 is then deposited to form the future gates of thetwo transistors in a conventional manner known in the art (FIG. 4).

After applying a resin mask 6 to protect the remainder of thesemiconductor wafer, the gate 5 is pre-implanted with polysilicon 7 sothat the conductivity of the gate material conforms to the type oftransistor to be made. In other words, in this instance, because the aimis to make two N-channel transistors (NMOS transistors), the gatematerial is doped with arsenic, for example, to confer N-typeconductivity on it.

The geometry of the future gates of the two transistors is then definedusing two resin blocks 8 in a conventional way known in the art (FIG.6). The polysilicon layer 5 is then etched on either side of the resinblocks 8 until the top surface of the substrate 1 is reached, as shownin FIG. 7, to form the gate 51 of the future transistor T1 with a thickoxide layer 401 and the gate 52 of the future transistor T2 with a thinoxide layer 402.

A first dopant 16 with a first concentration is then implanted in thewell 13 and in particular on either side of the gate 52 (FIGS. 8 and 9).Implanting the first dopant contributes to forming the low-doped sourceand drain areas of the future oxide transistor 20. N-type implantationis used in the case of an NMOS transistor (NLDD implantation). The firstdopant 16 is therefore arsenic As, for example. The concentration usedis 2×10¹⁴ cm⁻² and the implantation is effected at an energy of 50 keV.

Note that the first dopant 16 is implanted before forming the insulativelateral regions (spacers) of the thin oxide transistor. Also, the activearea of the other (thick oxide) transistor is protected duringimplantation by a resin layer 9.

After removing the resin layer 9, the configuration shown in FIG. 9 isobtained; FIG. 9 shows the low-doped implanted areas 17 of the futurethin oxide transistor; note the absence at this stage of low-doped areason either side of the gate 51 of the future thick oxide transistor.

A stack of insulative layers 18 formed of tetraethyl orthosilicate(TEOS), for example, is then deposited in a conventional manner that isknown in the art (FIG. 10) to a thickness of the order 200 Å, forexample, surmounted by a layer of silicon nitride with a thickness of800 Å, for example.

Etching the stack of layers 18 produces a gate 51 flanked by spacers 181and a gate 52 flanked by spacers 182.

After applying a layer of resin 19 to protect the remainder of thewafer, conventional implantation 21 is then carried out (FIG. 12) toform the high-doped drain and source regions of the two transistors. Theimplantation 21, intended to impart N⁺ conductivity to the source anddrain regions, is effected with arsenic at a concentration of 4×10¹⁵cm⁻² and at an energy of 60 keV, for example.

A second dopant 22 is then implanted simultaneously on both sides of theinsulative lateral regions (spacers) 181 and 182 associated with thegates 51 and 52 of the future transistors.

Although the second dopant can also be arsenic, it has been noted thatphosphorus is preferable for obtaining the effect that the presentinvention seeks to obtain, as it provides a less abrupt transition thanarsenic. The concentration of the second dopant 22 is of the order of10¹³ cm⁻², for example. Implantation is carried out at an energy of 40keV or less, for example.

The skilled person will have noted that implantation with the seconddopant forms the low-doped source and drain areas of the thick oxidetransistor T1. Because the implantation is effected on both sides of thespacers 181 in particular, it is oblique to enable the low-doped areasto extend under the spacers 181 of the transistor T1.

Note also that the implantation step 22 could have been carried outbefore the implantation step 21.

When the resin mask 19 is removed, the two transistors T1 and T2 shownin FIG. 13 are obtained; the compositions of their low-doped source anddrain areas and their high-doped source and drain regions will now bedescribed in more detail, with particular reference to FIGS. 14 and 15.

As shown in FIG. 15, the low-doped source and drain areas of the thickoxide transistor T1 are formed from the area 61 implanted withphosphorus. The area 61 is extended outside the spacer 181 by the N⁺region 21 highly doped with arsenic.

As for the thin oxide transistor T2 (FIG. 14), the N⁺ drain and sourceregion 72 highly doped with arsenic is extended under the spacer andunder the gate by the low-doped source and drain areas that here consistof the arsenic-doped area 17 and the additional implantation ofphosphorus 61.

The method according to the invention therefore produces a thick gateoxide transistor and a thin gate oxide transistor simultaneously,producing a gradual NLDD junction in the low-doped source and drainareas for the thick oxide transistor and retaining an abrupt NLDDtransition for the thin gate oxide transistor. The additionalimplantation of phosphorus 61 does not alter the abrupt nature of thetransition obtained by the arsenic implanting step 17.

Although with a conventional double gate oxide process a high leakagecurrent would be observed in the turned off state (zero gate voltage)and with a drain voltage of 5 V, there is now no leakage current at adrain voltage of 5 V in a thick oxide transistor obtained by theimproved double gate oxide process of the invention. The onset of aleakage current is pushed back for a drain voltage in the turned offstate of at least 7 V.

The invention is not limited to the embodiments described, butencompasses all variants thereof.

It would therefore have been possible, at the stage of the process shownin FIG. 8, to free the well 14 as well and to implant the second dopant(for example phosphorus at a low concentration) directly to form thelow-doped drain and source areas of the thick oxide transistor at thisstage. At this time, of course, the implantation would have to beoblique because it would be effected before forming the spacers.However, an embodiment of this kind would have subsequently necessitatedan additional resin mask to mask the well 14 of the thick oxidetransistor to perform the arsenic implantation 16 at a higher dose,completing the formation of the low-doped source and drain areas of thethin oxide transistor.

The embodiment shown in FIG. 8 therefore has the considerable advantageof not requiring the use of an additional reticle and an additionalspecific masking step to make the two transistors simultaneously. At theFIG. 8 stage, it is merely necessary to modify the design of the mask,to extend it at the level of the caisson 14; the mask, usually employedin a CMOS fabrication method, and known to the skilled person as an“NLDD mask”, protects the other areas of the wafer that are not to beimplanted.

Finally, although the invention is described in detail here forN-channel transistors, it also applies to the simultaneous production ofP-channel transistors. The skilled person will know how to make thenecessary modifications as to the conductivity types of the variousburied layers and wells to be used.

What is more, in the case of producing P-type transistors, the firstdopant 16 and the second dopant 22 can be boron, for example.

1. A method for simultaneously fabricating a pair of insulated gatetransistors comprising a first transistor having a thicker gate oxidelayer than a second transistor, for each of the first and the secondtransistor in the pair of insulated gate transistors, the methodcomprising: forming at least one gate oxide layer; forming at least onegate flanked by one or more insulative lateral regions; forming at leastone high-doped drain; forming one or more source regions; forming atleast one low-doped source area and a drain area extending under theinsulative lateral regions between the high-doped drain and the one ormore source regions; wherein the step of forming at least one low-dopedsource area and a drain area for a second transistor includes forming atleast one low-doped source area and a drain area by implanting a firstdopant having a first concentration and implanting a second dopanthaving a second concentration lower than the first concentration;wherein the step of forming at least one low-doped source area and adrain area for a first transistor includes forming a low-doped sourceand a drain by implanting the second dopant and by not implanting thefirst dopant; and wherein the step of forming at least one gate flankedby one or more insulative regions includes implanting the first dopanton either side of the gate of the second transistor prior to forming theinsulative lateral regions, and whereby an active area of the firsttransistor is protected by a layer of resin.
 2. The method according toclaim 1, wherein the step of forming at least one gate flanked by one ormore insulative regions includes implanting a second dopant obliquelyand simultaneously from either side of the insulative lateral regions ofeach of the first transistor and the second transistor.
 3. The methodaccording to claim 1, characterized in that the first transistor and thesecond transistor are N-channel transistors and in that the first dopantis arsenic and the second dopant is phosphorus.
 4. The method accordingto claim 1, characterized in that the first transistor and secondtransistor are P-channel transistors and in that the first dopant andthe second dopant are boron.
 5. The method according to claim 1, whereinthe step of forming at least one low-doped source area and drain areasfor a second transistor includes implanting a second dopant having asecond concentration in the order of 10¹³ cm⁻².
 6. The method accordingto claim 5, wherein the step of forming at least one low-doped sourcearea and drain areas for a second transistor includes implanting asecond dopant carried out at an energy of 40 keV or less.
 7. The methodaccording to claim 1, wherein the step of forming at least one low-dopedsource area and a drain area for a second transistor includes implantinga first dopant having a first concentration in the order of 2×10¹⁴ cm⁻².8. The method according to claim 7, wherein the step of forming at leastone low-doped source area and a drain area for a second transistorincludes implanting a first dopant at an energy of 50 keV .
 9. A methodfor simultaneously fabricating a pair of insulated gate transistorscomprising a first transistor having a thicker gate oxide layer than asecond transistor, the method comprising: forming for a first transistorand a second transistor; at least one gate oxide layer; at least onegate flanked by insulative lateral regions, whereby the insulativeregions includes implanting a first dopant on either side of the gate ofthe second transistor prior to forming the insulative lateral regions,and whereby an active area of the first transistor is protected by alayer of resin; at least one high-doped drain and one or more sourceregions; at least one low-doped source area and a drain area extendingunder the insulative lateral regions between the high-doped drain andthe one or more source regions by implanting the first dopant having afirst concentration and implanting a second dopant having a secondconcentration lower than the first concentration for the secondtransistor; and at least one low-doped source area and drain areaextending under the insulative lateral regions between the high-dopeddrain and the one or more source regions by implanting the second dopantand by not implanting the first dopant for the first transistor.